Journal/Conference Papers

[1] Sekedi Kobenge, Huazhong Yang, A 250 KS/s, “0.8 V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator,” IEICE Electronics Express, 2010, 7(4):261–267

[2] Bo Zhao, Xiaojian Mao, Huazhong Yang, Hui Wang, “A 1.41-1.72 GHz Sigma-Delta Fractional-N Frequency Synthesizer with a PVT Insensitive VCO and a New Prescaler”, Analog Integrated Circuits and Signal Processing, 2009.6, 59(3): 265-273

[3] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang and Yuan Xie, “Temperature-aware NBTI Modeling Techniques in Digital Circuits”, IEICE Trans. on Electronics, 2009.6, E92C(6): 875-886.

[4] Fei Qiao, Huazhong Yang, WANG Hui, “Low-standby-current and high-speed SAFF with improved conditional-precharge modules”, International Journal of Electronics, 2009.06, 96(6): 639–656.

[5] Saihua Lin, Huazhong Yang, Rong Luo, “A new family of sequential elements with built-in soft error tolerance for dual-VDD systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.10, 16(10): 1372-1384.

[6] Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang, “Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.09, 16(9):1101-1113.

[7] Hengyu Long, Yongpan Liu, Yiqun Wang, Robert Dick, Huazhong Yang, “Battery allocation for wireless sensor network lifetime maximization under cost constraints,” ICCAD 2009, San Jose, CA, pp.705-712

[8] Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang, “Energy Efficient Architecture of Sensor Network Node Based on Compression Accelerator,” GLSVLSI 2009, Boston, MA, pp.117-120

[9] Qian Ding; Yu Wang; Hui Wang; Rong Luo; Huazhong Yang; “Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths,” ISQED 2008, San Jose, CA, pp.74-77

[10] Yongpan Liu, Huazhong Yang, Robert Dick, Hui Wang, Li Shang, “Thermal vs Energy Optimization for DVFS-enabled Processors in Embedded Systems”, ISQED 2007, San Jose, CA, pp. 204-209

[11] Yoshitaka Ueda, Mayumi Fujisawa, Shinji Furuichi, Mamoru Mukuno, Hideki Yamauchi, Fei Qiao, Huazhong Yang, “6.33mW MPEG audio decoding on a multimedia processor,” ISSCC 2006, San Francisco, CA, pp.414-415, 662

[12] Xiaojian Mao, Huazhong Yang, Hui Wang, “Behavioral Modeling and Simulation of Jitter and Phase Noise in Fractional-N PLL Frequency Synthesizer,” IEEE BMAS 2004, San Jose, CA, pp.25-30

BOOKS

1. Yuyu Liu, Huazhong Yang, High-Speed Transceivers—Integrated Circuits Designs and Optical Device Techniques, World Scientific Pub. : Singapore, March 2006.

2. Huazhong Yang, Rong Luo, Hui Wang, Modeling Methodologies for System-on-Chip, Tsinghua Univ. Press : Beijing, 2003, In Chinese

3. Huazhong Yang, Hui Wang, Runsheng Liu, Automatic Synthesis Methodologies for Analog Integrated Circuits, Science Press : Beijing, 1999, In Chinese

4. Hui Wang, Huazhong Yang, Rong Luo, Computer Aided Analysis and Design Methods of Electric Circuits, Tsinghua Univ. Press : Beijing, 2008, In Chinese

Patents Issued by SIPO, China

1. Huazhong Yang, Tao Jiang, Bandgap Reference with Multiple Points Curvature Compensation, ZL200610114282.3,2008.10.22

2. Huazhong Yang, Hong Luo, Yu Wang, Rong Luo, Hui Wang, A Method of Reducing the Power of On-Chip Memories, ZL200610057124.9,2009.04.02

3. Huazhong Yang, Beihua Ying, Wei Liu, Yongpan Liu, Hui Wang, An Data-Compression Criterion for Power Reduction of Wireless Sensor Networks, ZL200810238934.3,2009.10.21

4. Sekedi Kobenge, Huazhong Yang, An Ultra Low Power Time-Domain Comparator, ZL200810114513.X, 2010.01.20

1. National Science and Technology Major Project, “RF and Baseband SoC for Medium and High Speed Wireless Sensor Network Nodes”, January 2010-December 2012, Principle Investigator

        Wireless sensor networks (WSN) have gain great momentum in recent years. The objective of the project is to integrate the RF transceiver, baseband and MAC processor, data compression, analog-to-digital converters for analog sensors and interface circuits into a single chip to reduce the energy consumption and cost of WSN nodes. Two prototype WSN networks will be realized to explore the application of the single chip solution of WSN nodes.

2. National Science and Technology Major Project, “Low Power Clock Tree Synthesis of High Performance Embedded CPUs”, January 2010-December 2011, Principle Investigator

        The objective of the project is to propose some new clock tree synthesis algorithms and to develop a prototype design tool of clock trees in CPUs. Compared with traditional clock tree tools, this prototype tool should reduce at least 10% power consumption of the clock tree.

3. National Science and Technology Major Project, “Low Power Techniques for Digital Signal Processors”, January 2009-December 2011, Co-principle Investigator

        The objective of the project is to reduce 10%-15% power consumption of a digital signal processor. Low power functional circuits, power management, and task scheduling will be addressed.

4. National Science and Technology Major Project, “Parallel Circuit Simulator and Waveform Viewer”, September 2008-December 2010, Co-principle Investigator

         The objective of the project is to design a parallel circuit simulator for multi-core computers and to develop an easy-to-use waveform viewer for analogy circuit designers.

5. IBM Shared University Research Project, “Application-Specific Architecture of Multi-core System with Hybrid Interconnection Networks”, September 2009- September 2011, Co-principle Investigator.

        This IBM SUR project focuses on the heterogeneous multi-core architecture with high performance and low power consumption for multimedia applications, especially the video processing applications, which would be cooperative with IBM’s internal multi-core architecture projects.

6. STMicroelectronics Sponsored Project, “Application Specific Integrated Circuits and Systems Design”, October 2003-December 2012, Principle Investigator

        The objective of the project is to create novel integrated circuit techniques and to develop single chip solutions to digital broadcasting, audio and video signal processing, measurement, and wireless sensors networks.

7. Hi-tech Research and Development Program of China (National 863 Program), “Low Power Techniques for Wireless Sensor Networks,” January 2006-December 2008, Principle Investigator.

        An adaptive data compression algorithm was proposed and integrated into a 0.18um CMOS chip, which could reduce about 98% energy consumption of traditional WSN nodes.

8. NSFC Key Project, “Low Power Design Methodology for System-on-Chip”, January 2003-December 2008, Principle Investigator.

        This project mainly focuses on the low-power architecture of systems-on-a-chip (SoC), system-level power management, low-power circuits, leakage power reduction methods, power modeling, and power optimization. Major progress we have achieved include, A) a set of conditional-precharge D-flip-flops in sense-amplifier topology, which can reduce more than 33% power without any loss in speed and area, B) an interconnect interface circuit with ultra-low voltage swing of 50mV which can be operated at 500MHz and reduce the power significantly, C) an alternative-current powered OpAmp applied in switched-capacitor circuits, D) leakage power reduction methods, such as input vector control, signal-path-level dual-Vt assignment, etc. and E) joint power and thermal analysis and optimization. The inconsistence between power optimal and thermal optimal is revealed, while a leakage power estimation algorithm considers the temperature effect and yields a 4-6 orders speed up over previous.

9. NSFC Funding for National Palmary Young Researchers, “Low Power Circuits and Systems”, January 2001-December 2004, Principle Investigator.

         Low power and system integration are two key aspects towards system-on-chip (SoC) addressed in this project. A soft-decision DAPSK modulation/demodulation scheme was proposed. The scheme is of higher resistance to noise and takes 25% less frequence bandwidth, compared with QAM. A novel principle on the partitioning of system timing domains is proposed and has been successfully applied to a channel demodulation chip of DAB receivers. Several low power functional cells were designed, including low power FFT, ultra-low-swing interface circuit for IP interconnection, low power D flip-flop (DFF). The DFF takes sense amplifier structure to gain high resistance to interference, while low-clock-swing and conditional-prechage are adopted to reduce its power consumption.

10. 973 Program, “Full-Chip Transistor-Level Timing Simulation Algorithms”, September 1999 – September 2004, Principle Investigator.

        The project focuses on fast and accurate timing calculation of huge-scale CMOS digital systems. A parallel transistor-level timing simulator, RSPICE, was developed. By partitioning the whole circuits into DCCBs and SCCs, RSPICE can simulate huge-scale circuit at transistor level. RSPICE is 1000x faster than SPICE by virtue of its unique table model and time-step control scheme, and the calculation error of RSPICE is less than 3-5%. RSPICE is also successfully applied to coupling noise estimation.

No content

No content

No content

No content