Academic Achievement

Journal/Conference Papers

[1] Sekedi Kobenge, Huazhong Yang, A 250 KS/s, “0.8 V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator,” IEICE Electronics Express, 2010, 7(4):261–267

[2] Bo Zhao, Xiaojian Mao, Huazhong Yang, Hui Wang, “A 1.41-1.72 GHz Sigma-Delta Fractional-N Frequency Synthesizer with a PVT Insensitive VCO and a New Prescaler”, Analog Integrated Circuits and Signal Processing, 2009.6, 59(3): 265-273

[3] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang and Yuan Xie, “Temperature-aware NBTI Modeling Techniques in Digital Circuits”, IEICE Trans. on Electronics, 2009.6, E92C(6): 875-886.

[4] Fei Qiao, Huazhong Yang, WANG Hui, “Low-standby-current and high-speed SAFF with improved conditional-precharge modules”, International Journal of Electronics, 2009.06, 96(6): 639–656.

[5] Saihua Lin, Huazhong Yang, Rong Luo, “A new family of sequential elements with built-in soft error tolerance for dual-VDD systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.10, 16(10): 1372-1384.

[6] Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang, “Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.09, 16(9):1101-1113.

[7] Hengyu Long, Yongpan Liu, Yiqun Wang, Robert Dick, Huazhong Yang, “Battery allocation for wireless sensor network lifetime maximization under cost constraints,” ICCAD 2009, San Jose, CA, pp.705-712

[8] Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang, “Energy Efficient Architecture of Sensor Network Node Based on Compression Accelerator,” GLSVLSI 2009, Boston, MA, pp.117-120

[9] Qian Ding; Yu Wang; Hui Wang; Rong Luo; Huazhong Yang; “Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths,” ISQED 2008, San Jose, CA, pp.74-77

[10] Yongpan Liu, Huazhong Yang, Robert Dick, Hui Wang, Li Shang, “Thermal vs Energy Optimization for DVFS-enabled Processors in Embedded Systems”, ISQED 2007, San Jose, CA, pp. 204-209

[11] Yoshitaka Ueda, Mayumi Fujisawa, Shinji Furuichi, Mamoru Mukuno, Hideki Yamauchi, Fei Qiao, Huazhong Yang, “6.33mW MPEG audio decoding on a multimedia processor,” ISSCC 2006, San Francisco, CA, pp.414-415, 662

[12] Xiaojian Mao, Huazhong Yang, Hui Wang, “Behavioral Modeling and Simulation of Jitter and Phase Noise in Fractional-N PLL Frequency Synthesizer,” IEEE BMAS 2004, San Jose, CA, pp.25-30


1. Yuyu Liu, Huazhong Yang, High-Speed Transceivers—Integrated Circuits Designs and Optical Device Techniques, World Scientific Pub. : Singapore, March 2006.

2. Huazhong Yang, Rong Luo, Hui Wang, Modeling Methodologies for System-on-Chip, Tsinghua Univ. Press : Beijing, 2003, In Chinese

3. Huazhong Yang, Hui Wang, Runsheng Liu, Automatic Synthesis Methodologies for Analog Integrated Circuits, Science Press : Beijing, 1999, In Chinese

4. Hui Wang, Huazhong Yang, Rong Luo, Computer Aided Analysis and Design Methods of Electric Circuits, Tsinghua Univ. Press : Beijing, 2008, In Chinese

Patents Issued by SIPO, China

1. Huazhong Yang, Tao Jiang, Bandgap Reference with Multiple Points Curvature Compensation, ZL200610114282.3,2008.10.22

2. Huazhong Yang, Hong Luo, Yu Wang, Rong Luo, Hui Wang, A Method of Reducing the Power of On-Chip Memories, ZL200610057124.9,2009.04.02

3. Huazhong Yang, Beihua Ying, Wei Liu, Yongpan Liu, Hui Wang, An Data-Compression Criterion for Power Reduction of Wireless Sensor Networks, ZL200810238934.3,2009.10.21

4. Sekedi Kobenge, Huazhong Yang, An Ultra Low Power Time-Domain Comparator, ZL200810114513.X, 2010.01.20


Doctoral degree

Huazhong YANG
MOBILE Version