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DOI码：10.1109/ICALIP.2008.4590003

发表刊物：International Conference on Audio, Language and Image ProcessingInternational Conference on Audio, Language and Image Processing

摘要：As the low cost, low power and low complexity are key points of the consumer application requirements, we propose a novel hardware-oriented architecture Of the inverse quantization (IQ) in this paper, one of the important units, in computational complexity and precision, for MPEG-1 layer III decoder. It achieves a high throughput with lower memory requirement and can be reused into other calculation environment. The proposed IQ module has been designed and implemented by using VLSI cell-based approach. With three-level pipeline architecture, the maximum operation frequency of the design is 60 MHz. For the IQ computation of one data sample, it requires 33-35 clock periods, so that provides 40% reductions compared to that performed on DSP. The die size is 2.2 x 2.2 mm(2), including 18K bits of internal SRAM, and has been manufactured in an umc 0.18um 1P6M CMOS process.

合写作者：Dellandrea, Emmanuel, Dou, Weibei, Chen, Liming,Ruan, Su, Chen, Yanping, Bloyet, Daniel, Constans, Jean-Marc

第一作者：Zhang, Xuanlei,Dou, Weibei, Ruan, Su, Chen, Yanping, Bloyet, Daniel, Constans, Jean-Marc

论文类型：会议论文

页面范围：247-251

是否译文：否

发表时间：2008-07-07